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| PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k Rev. 10 -- 15 November 2009 Product data sheet 1. Product profile 1.1 General description NPN/PNP Resistor-Equipped Transistors (RET). Table 1. Product overview Package NXP PEMD3 PIMD3 PUMD3 SOT666 SOT457 SOT363 JEITA SC-74 SC-88 PNP/PNP complement PEMB11 PUMB11 NPN/NPN complement PEMH11 PUMH11 Type number 1.2 Features Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs 1.3 Applications Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Symbol VCEO IO R1 R2/R1 Quick reference data Parameter collector-emitter voltage output current (DC) bias resistor 1 (input) bias resistor ratio Conditions open base Min 7 0.8 Typ 10 1 Max 50 100 13 1.2 Unit V mA k NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 2. Pinning information Table 3. Pin 1 2 3 4 5 6 Pinning Description GND (emitter) TR1 input (base) TR1 output (collector) TR2 GND (emitter) TR2 input (base) TR2 output (collector) TR1 1 2 3 001aab555 TR1 R2 R1 R1 R2 TR2 Simplified outline 6 5 4 Symbol 6 5 4 1 2 3 006aaa143 3. Ordering information Table 4. Ordering information Package Name PEMD3 PIMD3 PUMD3 SC-74 SC-88 Description plastic surface mounted package; 6 leads plastic surface mounted package; 6 leads plastic surface mounted package; 6 leads Version SOT666 SOT457 SOT363 Type number 4. Marking Table 5. PEMD3 PIMD3 PUMD3 [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China Marking codes Marking code[1] D3 M7 D*3 Type number PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 2 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCBO VCEO VEBO VI Parameter collector-base voltage collector-emitter voltage emitter-base voltage input voltage TR1 positive negative input voltage TR2 positive negative IO ICM Ptot output current (DC) peak collector current total power dissipation SOT363 SOT457 SOT666 Tstg Tj Tamb Per device Ptot total power dissipation SOT363 SOT457 SOT666 [1] [2] [3] Conditions open emitter open base open collector Min - Max 50 50 10 +40 -10 +10 -40 100 100 200 300 200 +150 150 +150 Unit V V V V V V V mA mA mW mW mW C C C Per transistor; for the PNP transistor with negative polarity Tamb 25 C [1] [2] [1][3] -65 -65 storage temperature junction temperature ambient temperature Tamb 25 C [1] [2] [1][3] - 300 600 300 mW mW mW Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. Device mounted on an FR4 PCB with 65 m copper strip line, standard footprint. Reflow soldering is the only recommended soldering method. PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 3 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 6. Thermal characteristics Table 7. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient SOT363 SOT457 SOT666 Per device Rth(j-a) thermal resistance from junction to ambient SOT363 SOT457 SOT666 [1] [2] [3] Conditions in free air [1] [2] [1][3] Min Typ Max Unit Per transistor - - 625 417 625 K/W K/W K/W in free air [1] [2] [1][3] - - 416 208 416 K/W K/W K/W Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Device mounted on an FR4 PCB with 65 m copper strip line, standard footprint. Reflow soldering is the only recommended soldering method. 7. Characteristics Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter ICBO ICEO collector-base cut-off current collector-emitter cut-off current emitter-base cut-off current DC current gain collector-emitter saturation voltage Conditions VCB = 50 V; IE = 0 A VCE = 30 V; IB = 0 A VCE = 30 V; IB = 0 A; Tj = 150 C VEB = 5 V; IC = 0 A VCE = 5 V; IC = 5 mA IC = 10 mA; IB = 0.5 mA Min 30 2.5 7 0.8 VCB = 10 V; IE = ie = 0 A; f = 1 MHz Typ 1.1 1.8 10 1 Max 100 1 50 400 150 0.8 13 1.2 2.5 3 pF pF mV V V k Unit nA A A A Per transistor; for the PNP transistor with negative polarity IEBO hFE VCEsat VI(off) VI(on) R1 R2/R1 Cc off-state input voltage VCE = 5 V; IC = 100 A on-state input voltage VCE = 0.3 V; IC = 10 mA bias resistor 1 (input) bias resistor ratio collector capacitance TR1 (NPN) TR2 (PNP) PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 4 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 103 hFE (1) (2) (3) 006aaa034 1 006aaa035 VCEsat (V) 102 10-1 (1) (2) (3) 10 1 10-1 1 10 IC (mA) 102 10-2 1 10 IC (mA) 102 VCE = 5 V (1) Tamb = 150 C (2) Tamb = 25 C (3) Tamb = -40 C IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C Fig 1. TR1 (NPN): DC current gain as a function of collector current; typical values 10 006aaa036 Fig 2. TR1 (NPN): Collector-emitter voltage as a function of collector current; typical values 10 006aaa037 VI(on) (V) (1) (2) VI(off) (V) (1) 1 (3) 1 (2) (3) 10-1 10-1 1 10 IC (mA) 102 10-1 10-2 10-1 1 IC (mA) 10 VCE = 0.3 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C VCE = 5 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C Fig 3. TR1 (NPN): On-state input voltage as a function of collector current; typical values Fig 4. TR1 (NPN): Off-state input voltage as a function of collector current; typical values PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 5 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k -103 006aaa046 -1 006aaa047 hFE (1) VCEsat (V) (2) -102 (3) -10-1 (1) (2) -10 (3) -1 -10-1 -1 -10 IC (mA) -102 -10-2 -1 -10 IC (mA) -102 VCE = -5 V (1) Tamb = 150 C (2) Tamb = 25 C (3) Tamb = -40 C IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C Fig 5. TR2 (PNP): DC current gain as a function of collector current; typical values 006aaa048 Fig 6. TR2 (PNP): Collector-emitter voltage as a function of collector current; typical values 006aaa049 -102 VI(on) (V) -10 -10 VI(off) (V) (1) (1) (2) -1 (2) (3) -1 (3) -10-1 -10-1 -1 -10 IC (mA) -102 -10-1 -10-2 -10-1 -1 IC (mA) -10 VCE = -0.3 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C VCE = -5 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C Fig 7. TR2 (PNP): On-state input voltage as a function of collector current; typical values Fig 8. TR2 (PNP): Off-state input voltage as a function of collector current; typical values PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 6 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 8. Package outline 2.2 1.8 6 5 4 0.45 0.15 1.1 0.8 6 3.1 2.7 5 4 0.6 0.2 1.1 0.9 2.2 1.35 2.0 1.15 pin 1 index 3.0 2.5 1.7 1.3 pin 1 index 1 0.65 1.3 Dimensions in mm 2 3 0.3 0.2 0.25 0.10 06-03-16 1 0.95 1.9 Dimensions in mm 2 3 0.40 0.25 0.26 0.10 04-11-08 Fig 9. Package outline SOT363 (SC-88) 1.7 1.5 6 5 Fig 10. Package outline SOT457 (SC-74) 0.6 0.5 4 0.3 0.1 1.7 1.5 1.3 1.1 pin 1 index 1 0.5 1 Dimensions in mm 2 3 0.27 0.17 0.18 0.08 04-11-08 Fig 11. Package outline SOT666 PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 7 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 9. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description PEMD3 PIMD3 PUMD3 SOT666 SOT457 SOT363 2 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel; T1 4 mm pitch, 8 mm tape and reel; T2 4 mm pitch, 8 mm tape and reel; T1 4 mm pitch, 8 mm tape and reel; T2 [1] [2] [3] [2] [3] [2] [3] Packing quantity 3000 4000 -115 -125 -115 -125 -115 8000 10000 -315 -135 -165 -135 -165 For further information and the availability of packing methods, see Section 12. T1: normal taping T2: reverse taping PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 8 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 10. Revision history Table 10. Revision history Release date Data sheet status Product data sheet Change notice Supersedes PEMD3_PIMD3_ PUMD3_9 Document ID Modifications: PEMD3_PIMD3_ PUMD3_10 20091115 * * This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. Figure 9 "Package outline SOT363 (SC-88)": updated Product data sheet Product data sheet PEMD3_PIMD3_ PUMD3_8 PEMD3_PUMD3_7 PEMD3_PIMD3_ PUMD3_9 PEMD3_PIMD3_ PUMD3_8 20050518 20041206 PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 9 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 11. Legal information 11.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PEMD3_PIMD3_PUMD3_10 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 10 -- 15 November 2009 10 of 11 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k 13. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Packing information . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 November 2009 Document identifier: PEMD3_PIMD3_PUMD3_10 |
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